Conventionally, the speed of a semiconductor integrated circuit, particularly a flip-flop circuit, is increased by incorporating a dynamic circuit into its internal structure as described in, for example, Patent Document 1. The dynamic flip-flop circuit described in Patent Document 1 has a function of receiving a plurality of pieces of data, selecting any one of them, and holding and outputting the selected data.
Hereinafter, the structure of the flip-flop circuit having the data selection function will be described with reference to FIG. 3(a). In FIG. 3(a), a data selection circuit 91 is provided at the previous stage of a holding circuit 90. In the data selection circuit 91, when a clock CLK is at a Low level (Low period), a node N1 is precharged to a power source potential Vdd by a p-type transistor Tr1, while a node N2 is precharged to the power source potential Vdd by a p-type transistor Tr50. Near the end of this period, one of selection signals S0 to S2 which is used to select any one of a plurality of pieces of data D0 to D2 is turned High. Subsequently, when the clock CLK goes to High and the selected data (e.g., D0) is High, the electric charge of the node N1 is discharged via an n-type transistor Tr2, so that the potential of the node N1 becomes equal to that of the ground. Therefore, an n-type transistor Tr51 is turned OFF, so that the precharge potential of the node N2 is held. In this case, this potential is held as an H value by the holding circuit 90, which in turn outputs an output signal Q having the H value.
On the other hand, when the selected data D0 is Low, the electric charge of the node N1 is not discharged, so that the potential of the node N1 is held as it is the precharge potential and the n-type transistor Tr51 is turned ON. As a result, the electric charge of the node N2 is discharged via the n-type transistor Tr51 and the n-type transistor Tr2, so that the potential of the node N2 becomes an L value. The L value is held by the holding circuit 90, which in turn outputs an output signal Q having the L value.
Note that, in FIG. 3(a), SI indicates a data input when scanning is performed, SE indicates a scan shift control signal, and SEB indicates an inverted signal of the scan shift control signal.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 20034-060497